1. Field of the Invention
The embodiments discussed herein are related to a semiconductor device and a method of manufacturing a semiconductor device.
2. Description of the Related Art
FIG. 8 is a cross-sectional view of a first example of a conventional semiconductor device. As depicted in FIG. 8, the semiconductor device includes an n-type silicon carbide semiconductor layer 102 on a front surface of an n+-type silicon carbide semiconductor substrate 101. Plural p-type semiconductor regions 103 are disposed in a surface region of the n-type silicon carbide semiconductor layer 102. An n+-type source region 104 and a p+-type contact region 105 are disposed in a surface region of the p-type semiconductor region 103. A gate electrode 107 is disposed through a gate insulating film 106 on the p-type semiconductor region 103 between the n+-type source region 104 and the n-type silicon carbide semiconductor layer 102. A source electrode 108 contacts the n+-type source region 104 and the p+-type contact region 105. A drain electrode 109 is disposed on a back surface of the n+-type silicon carbide semiconductor substrate 101 (see, for example, Japanese Laid-Open Patent Publication No. 2013-187302).
FIG. 9 is a cross-sectional view of a second example of the conventional semiconductor device. As depicted in FIG. 9, the semiconductor device includes an n-type silicon carbide semiconductor layer 202 on a front surface of an n+-type silicon carbide semiconductor substrate 201. Plural p+-type base regions 210 are disposed in a surface region of the n-type silicon carbide semiconductor layer 202. A p+-type silicon carbide semiconductor layer 211 is disposed on the p+-type base region 210 and the n-type silicon carbide semiconductor layer 202. In the p+-type silicon carbide semiconductor layer 211, an n-type semiconductor region 212 is disposed on the n-type silicon carbide semiconductor layer 202 between the p+-type base region 210 and the p+-type base region 210 that are adjacent to each other. In the p+-type silicon carbide semiconductor layer 211, a p-type semiconductor region 203, an n+-type source region 204, and a p+-type contact region 205 are disposed on the p+-type base regions 210. A gate electrode 207 is disposed through a gate insulating film 206 on the p-type semiconductor region 203 between the n+-type source region 204 and the n-type semiconductor region 212. A source electrode 208 contacts the n+-type source region 204 and the p+-type contact region 205. A drain electrode 209 is disposed on a back surface of the n+-type silicon carbide semiconductor substrate 201 (see, for example, Japanese Laid-Open Patent Publication No. 2013-102106).